The present invention relates generally to semiconductor devices, and more particularly to utilizing strained silicon-on-insulator (SSOI) substrates for nFET regions with strain release in pFET regions.
A complementary metal oxide semiconductor device (CMOS) uses complementary and symmetrically-oriented pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) arranged on silicon or silicon on insulator (SOI) substrates. A MOSFET, which is used for amplifying or switching electronic signals for logic functions, has source and drain regions connected by a channel. The source region is a terminal through which current in the form of majority charge carriers electrons or holes enters the channel, and the drain region is a terminal through which current in the form of majority charge carriers leaves the channel. In a p-type MOSFET (hereinafter “pFET”), the majority charge carriers are holes that flow through the channel, and in an n-type MOSFET (hereinafter “nFET”), the majority charge carriers are electrons that flow through the channel. A gate overlies the channel and controls the flow of current between the source and drain regions. The channel may be defined by a thin “fin” that provides more than one surface through which the gate controls the flow of current, thereby making the pFETs and nFETs “finFET” devices. Generally, the length of the fin is several orders of magnitude greater than the width.
Substrates used in the fabrication of pFETs and nFETs may comprise strained silicon on insulator (SSOI) substrates. Such substrates generally have intrinsic tensile stresses of several giga-Pascals (GPa), which generally improves electron mobility, thereby improving device performance. The strain in these substrates allows for improvement in device performance without a degradation in electrostatic characteristics even in short-channel finFET devices where the length and the width of the channel is short compared to those of typical planar MOSFETs. The channel length in finFET devices can be reduced compared to planar MOSFETs because of its improved gate control but the width can be the same.